sixteen bits adder...

L

light

Guest
hi
can someone help me?


module full_adder(s,cout,a,b,cin);
input a,b,cin;
output s,cout;

assign s=(a^b)^cin
assign cout=((a^b)&cin)|(a&b);

endmodule


//-----------------------------------


module 16_bits_adder(S,Cout,A,B,Cin);
input [15:0] A,B;
input Cin;
output [15:0] S;
output Cout;
wire c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,13,c14,15

full_adder(S[0],c1,A[0],B[0],Cin);
full_adder(S[1],c2,A[1],B[1],c1);
full_adder(S[2],c3,A[2],B[2],c2);
full_adder(S[3],c4,A[3],B[3],c3);
full_adder(S[4],c5,A[4],B[4],c4);
full_adder(S[5],c6,A[5],B[5],c5);
full_adder(S[6],c7,A[6],B[6],c6);
full_adder(S[7],c8,A[7],B[7],c7);
full_adder(S[8],c9,A[8],B[8],c8);
full_adder(S[9],c10,A[9],B[9],c9);
full_adder(S[10],c11,A[10],B[10],c10);
full_adder(S[11],c12,A[11],B[11],c11);
full_adder(S[12],c13,A[12],B[12],c12);
full_adder(S[13],c14,A[13],B[13],c13);
full_adder(S[14],c15,A[14],B[14],c14);
full_adder(S[15],Cout,A[15],B[15],c15);


endmodule

//-------------------------------------------

module test;
reg [15:0] A,B;
reg Cin;module full_adder(s,cout,a,b,cin);
input a,b,cin;
output s,cout;

assign s=(a^b)^cin
assign cout=((a^b)&cin)|(a&b);

endmodule


//-----------------------------------


module 16_bits_adder(S,Cout,A,B,Cin);
input [15:0] A,B;
input Cin;
output [15:0] S;
output Cout;
wire c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,13,c14,15

full_adder(S[0],c1,A[0],B[0],Cin);
full_adder(S[1],c2,A[1],B[1],c1);
full_adder(S[2],c3,A[2],B[2],c2);
full_adder(S[3],c4,A[3],B[3],c3);
full_adder(S[4],c5,A[4],B[4],c4);
full_adder(S[5],c6,A[5],B[5],c5);
full_adder(S[6],c7,A[6],B[6],c6);
full_adder(S[7],c8,A[7],B[7],c7);
full_adder(S[8],c9,A[8],B[8],c8);
full_adder(S[9],c10,A[9],B[9],c9);
full_adder(S[10],c11,A[10],B[10],c10);
full_adder(S[11],c12,A[11],B[11],c11);
full_adder(S[12],c13,A[12],B[12],c12);
full_adder(S[13],c14,A[13],B[13],c13);
full_adder(S[14],c15,A[14],B[14],c14);
full_adder(S[15],Cout,A[15],B[15],c15);


endmodule

//-------------------------------------------

module test;
wire [15:0] S;
wire Cout;

initial begin
A[15:0]=16\'b1110_0110_1101_0000;
B[15:0]=16\'b0100_1011_1011_1010;
Cin=1\'b0;
16_bits_adder(S,Cout,A,B,Cin);
$display(\"A is %b\",A);
$display(\"B is %b\",B);
$display(\"A+B is %b\",S);
end
endmodule



thanks.
 
What\'s the question?

On Saturday, October 29, 2022 at 7:08:05 AM UTC-7, light wrote:
hi
can someone help me?


module full_adder(s,cout,a,b,cin);
input a,b,cin;
output s,cout;

assign s=(a^b)^cin
assign cout=((a^b)&cin)|(a&b);

endmodule


//-----------------------------------


module 16_bits_adder(S,Cout,A,B,Cin);
input [15:0] A,B;
input Cin;
output [15:0] S;
output Cout;
wire c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,13,c14,15

full_adder(S[0],c1,A[0],B[0],Cin);
full_adder(S[1],c2,A[1],B[1],c1);
full_adder(S[2],c3,A[2],B[2],c2);
full_adder(S[3],c4,A[3],B[3],c3);
full_adder(S[4],c5,A[4],B[4],c4);
full_adder(S[5],c6,A[5],B[5],c5);
full_adder(S[6],c7,A[6],B[6],c6);
full_adder(S[7],c8,A[7],B[7],c7);
full_adder(S[8],c9,A[8],B[8],c8);
full_adder(S[9],c10,A[9],B[9],c9);
full_adder(S[10],c11,A[10],B[10],c10);
full_adder(S[11],c12,A[11],B[11],c11);
full_adder(S[12],c13,A[12],B[12],c12);
full_adder(S[13],c14,A[13],B[13],c13);
full_adder(S[14],c15,A[14],B[14],c14);
full_adder(S[15],Cout,A[15],B[15],c15);


endmodule

//-------------------------------------------

module test;
reg [15:0] A,B;
reg Cin;module full_adder(s,cout,a,b,cin);
input a,b,cin;
output s,cout;

assign s=(a^b)^cin
assign cout=((a^b)&cin)|(a&b);

endmodule


//-----------------------------------


module 16_bits_adder(S,Cout,A,B,Cin);
input [15:0] A,B;
input Cin;
output [15:0] S;
output Cout;
wire c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,13,c14,15

full_adder(S[0],c1,A[0],B[0],Cin);
full_adder(S[1],c2,A[1],B[1],c1);
full_adder(S[2],c3,A[2],B[2],c2);
full_adder(S[3],c4,A[3],B[3],c3);
full_adder(S[4],c5,A[4],B[4],c4);
full_adder(S[5],c6,A[5],B[5],c5);
full_adder(S[6],c7,A[6],B[6],c6);
full_adder(S[7],c8,A[7],B[7],c7);
full_adder(S[8],c9,A[8],B[8],c8);
full_adder(S[9],c10,A[9],B[9],c9);
full_adder(S[10],c11,A[10],B[10],c10);
full_adder(S[11],c12,A[11],B[11],c11);
full_adder(S[12],c13,A[12],B[12],c12);
full_adder(S[13],c14,A[13],B[13],c13);
full_adder(S[14],c15,A[14],B[14],c14);
full_adder(S[15],Cout,A[15],B[15],c15);


endmodule

//-------------------------------------------

module test;
wire [15:0] S;
wire Cout;

initial begin
A[15:0]=16\'b1110_0110_1101_0000;
B[15:0]=16\'b0100_1011_1011_1010;
Cin=1\'b0;
16_bits_adder(S,Cout,A,B,Cin);
$display(\"A is %b\",A);
$display(\"B is %b\",B);
$display(\"A+B is %b\",S);
end
endmodule



thanks.
 
Make it ready and send it back, it doesn\'t seem to be a question. Stackoverflow would be beneficial for you.
 

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